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| VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 Features * 17 Input by 17 Output Crosspoint Switch * 2.5Gb/s NRZ Data Bandwidth * 42 Gb/s Aggregate Bandwidth * TTL Compatible P Interface * Differential PECL Data Inputs 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring * On-chip 50 Input Terminations * 50 Source Terminated PECL Output Drivers * Single 3.3V Supply * 9W Maximum Power Dissipation * High Performance 256 Pin BGA Package General Description The VSC834 is a monolithic 17x17 asynchronous crosspoint switch designed to carry broadband data streams at up to 2.5Gb/s. The non-blocking switch core is programmed through a parallel microprocessor interface that allows random access programming of each output port. A high degree of signal integrity is maintained through the chip through fully differential signal paths. The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 17:1 multiplexer tree that can be programmed to one and only one of its 17 inputs, and each data input can be programmed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each input channel has an activity monitor function that can be used to identify loss of activity (LOA). An interrupt pin is provided to signal LOA, after which an external controller can query the chip to determine the channel(s) on which the fault occurred. Each output driver is a fully differential switched current driver with on-die back-terminations for maximum signal integrity. Data inputs are terminated on die through 50 resistors connected to VTERM. The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with a microprocessor-style interface. The control port provides access to all chip functions, including LOA, and programming. Program buffering is provided to allow multiple program assignments to be queued and issued simultaneously via a single configure command. VSC834 Block Diagram A0 Y0 A16 Control Logic P Interface Y16 G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Figure 1: Detailed Block Diagram: Datasheet VSC834 A, AN[16:0] LOA Monitor 17 Program Memory Output Drivers 17x17 Switch Core Y, YN[16:0] Control Interface DATA[4:0], ADDR[5:0] ALE, CSB, WRB, RDB INTB, MONCLK, CONFIG Functional Description Data Paths All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a nominal impedance of 50. All input termination resistors are tied to VTERM. Data outputs are provided through differential current switches with on-chip terminations that produce a PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels when terminated in 50 to 2.0V. Other termination voltages are possible, such as to VCC or 1.3V, but the voltage level of the output swing will be shifted from its nominal value. The common-mode voltage of the output swing can be adjusted using the VCOM pin. The adjustment range is not calibrated, but typically allows for about +200mV of adjustment in the output common-mode voltage. Output channels can be powered off in pairs if fewer than 17 outputs are required. By connecting the VEE pin associated with a given pair of outputs to VCC, the output pairs will pull to VCC and chip power will be reduced by roughly 200mW. Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Programming Interface The switch core is programmed through a parallel interface circuit that allows random reads or writes to the program memory array. The program memory array is buffered to allow multiple programming instructions to be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate. The program data is composed of two parts: output address and input address. The output address, denoted by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[4:0], specifies which input port the switch slice should connect to. The format of the program data is simple binary, where the binary value maps directly to the switch slice position and/or input port number. For example: ADDR[5:0] (000100) / DATA[4:0] (00110) would direct output channel Y4 to connect to input channel A6. The programming state may be verified (read back) by applying the address of the desired output and asserting RDB. The programming state is unknown at power-on. Additional address space is provided for access to the monitor registers (See Table 2). The microprocessor interface consists of the following signals. Levels are TTL (see Table 6). Table 1: Signal Table Pin D[5:0] A[5:0] ALE CSB WRB RDB INTB I/O B I I I I I O Description Bidirectional data bus to transfer data to/from internal program registers Address bus to select internal program registers for read-write operations Address Latch Enable: for use with multiplexed address/data buses. Latches the address bus internally when low. Chip Select (Active Low): assert this pin whenever the part is being read or programmed. Write (Active Low): program data will be transferred to the first level internal registers on the rising edge of this signal (when CSB is also low). Read (Active Low): program data from the internal program or monitor registers will be read out on the data bus when this signal goes low (with CSB also low). Interrupt (Active Low): this signal is asserted when an LOA condition is found Configure (Active High): assert this signal to transfer queued program information from the first-level internal registers to the second-level registers, making the programming take effect. This signal may be tied high to leave the second-level registers transparent so all programming will take effect immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a highorder bit of the address bus Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not expected to exceed 3MHz. CONFIG I MONCLK I Loss of Activity (LOA) Monitoring The LOA function consists of an activity monitor on each input channel, connected directly to the pads. The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying the address (See Table 2) of the monitor register corresponding to the signal of interest and asserting RDB. Each monitor register is four bits in length, covering the state of four inputs or outputs. There is one extra one-bit monitor for each of the 17th input and 17th output. The state of each monitor is transferred to the register periodically on the rising edge of MONCLK, whereupon the activity monitor is clered until more activity is detected. G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Datasheet VSC834 If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrupt will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read. The LOA circuitry requires a minimum signal level of 30-150 mV peak-peak to recognize an input as active. This is required to distinguish noise on an unconnected signal (where both inputs float to the termination voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal level can be adjusted with the VHYS pin, which can set the threshold from zero to the maximum allowed input swing. The VHYS pin will self-bias to a nomial value that will be appropriate for most applications (30-150mV p-p input level). Although uncalibrated for nominal level, gain and linearity, the VHYS pin can be externally set to adjust the threshold level over the entire range of the input signal, from zero to the maximum level allowed at the input. Table 2: Memory Map Address 00h 01h ... 10h 11h ... 20h 21h 22h 23h 24h 25h Access R/W R/W ... R/W R/W ... R/W R/O R/O R/O R/O R/O Output Y1's programmed input channel ... Output Y16's programmed input channel Description Output Y0's programmed input channel ( write and then assert CONFIG to program) Internal output Y17's programmed input channel ... Internal output Y32's programmed input channel Rx Activity monitor for inputs A0, A1,A2,A3 Rx Activity monitor for inputs A4, A5,A6,A7 Rx Activity monitor for inputs A8, A9,A10,A11 Rx Activity monitor for inputs A12, A13,A14,A15 Rx Activity monitor for input A16 ( Logic `1'=No activity) Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 AC Characteristics Table 3: Data Path Parameter FRATE TISKW TOSKW tR, tF tR, tF tjP Data rate Input channel delay skew (1) Output channel delay skew (2) High-speed input rise/fall times, 20% to 80% (3) High-speed output rise/fall times, 20% to 80% Output data eye jitter, peak-peak, 223 PRBS (4) 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Description Min - Typ 300 300 - Max 2.5 150 150 100 Units Gb/s ps ps ps ps ps Note: Unless otherwise stated, all specifications are guaranteed but not tested. Note 1: Skew between any two input channels to a given output. Note 2: Skew between any two output channels from the same input channel. Note 3: Required for high-speed output rise/fall spec at FRATE=2.5 Gbits/s. For lower rate signals, use 0.375/FRATE Note 4: Broadband jitter added to a jitter-free signal; jitter is primarily in the form of ISI for random data Figure 2: Interrupt Timing (Change in Monitor State Registers) MONCLK Monitor State Monitor State Reg INTB CSB RDB TsRDB ThRDB TtsDATA ADDR[5:0] DATA[4:0] Figure 3: Interrupt Timing (No Change in Monitor State Registers) MONCLK Monitor State Monitor State Reg INTB G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Figure 4: Program Timing Datasheet VSC834 ADDR[5:0] DATA[4:0] CSB WRB RDB CONFIG TsCONFIG TsCSB TsWRB ThWRB Table 4: Programing Port Interface Timing Parameter Tconfig TpdADDR TpdRDB Tpdint Tpdstate TsRDB ThRDB TsWRB ThWRB TsCONFIG TsCSB TpwCONFIG TpwWRB TpwRDB TtsDATA TsALE Switch configuration delay Data read propagation delay from ADDR Data read propagation delay from RDB (1) Interrupt propagation delay from MONCLK (2) MONCLK to internal state register change delay (2) ADDR to RDB setup time RDB to ADDR hold time WRB setup time (for either ADDR or DATA) WRB hold time (for either ADDR or DATA) WRB to CONFIG setup time CSB setup time (to either WRB or RDB) CONFIG pulse width (high) WRB pulse width (low and high) RDB pulse width (low and high) DATA tri-state delay (from either RDB or CSB) (2) ALE setup time (for multiplexed ADDR/DATA bus) Description Min 5 3 5 3 1 0 10 10 10 5 Max 6 30 7 50 6 10 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Measured from falling edge. Note 2: Measured from rising edge. Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 Table 5: Power Parameter ICC PT ITERM-V ITERM-E 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring DC Characteristics (All Characteristics Are Over The Specified Operating Conditions) Description VCC supply current Total chip power (VCC = 3.45V and +85C case) VTERM supply current with VTERM =VCC-1.3V VTERM supply current with VTERM =VCC-2.0V Min Typ Max 2600 9 ~0 -600 Units mA W mA mA Conditions Note: ICC Specified with outputs terminated with 50 to +2.0V and Chip VTERM=+2.0V. Table 6: Control Port Input Levels Parameter VVCOM VVHYS VIH VIL IIH IIL IOZ Description VCOM bias voltage (L and R) VHYS bias voltage Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Tristate output current (TTL) Min Typ 2.0 1.65 Max Units V V Conditions VCC=3.3V VCC=3.3V -- -- VIN = 2.4V VIN = 0.5V VOUT = 0.4V-2.4V 2.0 0 -- -- -100 -- -- -- -- -- 3.5 0.8 500 -500 100 V V A A A Table 7: Data Input Levels (Differential PECL) Parameter VID VICM Description Input differential voltage Input common-mode voltage Min 200 1.8 Typ -- -- Max 1000 2.2 Units mV V -- Conditions VCC=3.3V Table 8: Data Output Levels (Differential PECL) Parameter VOD VOCM Description Output differential voltage Output common-mode voltage Min 600 1.8 Typ -- -- Max 1000 2.2 Units mV V Conditions Note 1 Note 1 NOTE: (1) Nominal PECL mode, VCC=VCCP=3.3V, VEE=0, terminated 50 to +2.0V. G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Datasheet VSC834 Absolute Maximum Ratings Power Supply Voltage (VCC) Potential to GND ............................................................................-0.5 V to +4.0 V TTL Input Voltage Applied ..................................................................................................-0.5 V to VCC +0.5 V ECL Input Voltage Applied ..................................................................................................-0.5 V to VCC +0.5 V Output Current (IOUT) ................................................................................................................................... 50 mA Input Current (IIN) ...................................................................................................................................... 50 mA VTERM Current (ITERM) ............................................................................................................................ 800 mA Case Temperature Under Bias (TC) ............................................................................................. -55oC to + 125oC Storage Temperature (TSTG) ....................................................................................................... -65oC to + 150oC Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply voltage (VEE) ......................................................................................................................................... 0 V Supply voltage (VCC) .............................................................................................................................+3.3V 5% Supply voltage (VCCP) ...........................................................................................................................+3.3V 5% Termination voltage (VTERM)..................................................................................................................VCC -1.3V Case Temperature Operating Range (T).............................................................................................. 0oC to 85oC Junction Temperature Operating Range (TJ) .................................................................................... 0oC to 110oC ESD Ratings Proper ESD procedures should be used when handling this product. The VSC834 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1000V. Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 I/O Equivalent Circuits 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring VCC VCC VTERM VCC VCC 15 VCC 50 Pad Pad 50 50 Pad iSIG iSIG PECL Input Equivalent Circuit PECL Output Equivalent Circuit VCC VCC VCC VCC 1.3k Pad (On-die bias network) 2k Pad 25k 5k (On-die bias network) 5k VEE VCOM (L or R) Input Equivalent Circuit VHYS (C or L) Input Equivalent Circuit VEE G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 9 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Datasheet VSC834 Package Pin Descriptions The VSC834 is packaged in a 27x27mm 256 pin ball grid array package. The 256 BGA package is thermally enhanced and carries the high-speed signals over controlled impedance lines from the solder ball to the circuit die. The following sections describe the pinout and mechanical details of the VSC834. Figure 5: Functional Pinout Floorplan Programming Interface A0 A2 A4 A16 I/P LOA and Termination Control Logic Y0 17:1 Switch Slice Pair 17:1 Switch Slice Pair Y1 Y2 17:1 Switch Slice Pair 17:1 Switch Slice Pair Y3 17:1 Switch Slice Pair Y15 Y16 17:1 Switch Slice Pair I/P LOA and Termination Control Logic A1 A3 A5 A15 Programming Interface Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Figure 6: Pinout Diagram 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BALL GRID INDEX A ALE MONCLK A0 A6 A12 ADR0 ADR3 B ADR2 ADR4 C A2 A4 A8 A10 A14 A16 ADR1 ADR5 D E F Y0 Y2 Y4 Y6 VCC Y1 G VEE VTERM Y3 Y5 Y7 H J K L Y8 Y10 Y12 Y14 Y16 BOTTOM VIEW Y9 Y11 Y13 Y15 M N P R T VCOML D2 INTB U D0 VHYS VCOMR V A3 A5 A9 A11 A15 D1 D3 D5 D4 RDB CONFIG W WRB CSB Y A1 A7 A13 G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 11 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Datasheet VSC834 Table 9: Pin Identification Signal Name Pin High Speed Data Inputs A0, NA0 A1, NA1 A2, NA2 A3, NA3 A4, NA4 A5, NA5 A6, NA6 A7, NA7 A8, NA8 A9, NA9 A10, NA10 A11, NA11 A12, NA12 A13, NA13 A14, NA14 A15, NA15 A16, NA16 A15, A14 Y15, Y14 D14, C14 U14, V14 C13, D13 V13, U13 A13, A12 Y13, Y12 D12, C12 U12, V12 C11, D11 V11, U11 A11, A10 Y11, Y10 D10, C10 U10, V10 C9, D9 Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Function Level High Speed Data Outputs Y0, YN0 Y1, YN1 Y2, YN2 Y3, YN3 Y4, YN4 Y5, YN5 Y6, YN6 Y7, YN7 Y8, YN8 Y9, YN9 Y10, YN10 Y11, YN11 Y12, YN12 Y13, YN13 Y14, YN14 Y15, YN15 G18, G17 G1, H1 G20, H20 H4, H3 H17, H18 J3, J4 J18, J17 J1, K1 L20, M20 M4, M3 M17, M18 N3, N4 N18, N17 N1, P1 N20, P20 P4, P3 Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Page 12 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 Table 9: Pin Identification Signal Name Y16, YN16 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Pin P17, P18 Function Data Output Level PECL Programming Port ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 D0 D1 D2 D3 D4 D5 ALE INTB RDB WRB CONFIG CSB MONCLK B8 D8 C8 B7 C7 D7 V7 V8 U8 W8 Y8 Y9 A7 U7 W7 Y7 W6 Y6 A6 Program data address Program data address Program data address Program data address Program data address Program data address Program data Program data Program data Program data Program data Program data Address latch enable (active high) Interrupt (active low) Read enable (active low) Write enable (active low) Configuration strobe (active high) Chip select (active low) Loss of activity monitor clock (active high) TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Supplies A1, A2, A3, A4, A5, A16, A17, A18, A19, A20, B1, B2, B3, B4, B5, B15, B16, B17, B18, B19, B20, C1, C2, C3, C4, C5, C6, C16, C17, C18, C19, C20, D1, D2, D3, D4, D5, D16, D17, D18, D19, D20, E1, E2, E3, E4, E17, E18, E19, E20, F1, F2, F3, F4, F19, F20, G3, G4, G19, H2, J20, K2, K3, K4, K17, K18, K19, K20, L1, L2, L3, L4, L17, L18, L19, M1, P2, R1, R2, R4, R17, R18, R20, T1, T2, T3, T4, T17, T18, T19, T20, U1, U2, U3, U4, U16, U17, U18, U19, U20, V1, V2, V3, V4, V16, V17, V18, V19, V20, W1, W2, W3, W4, W5, W16, W17, W18, W19, W20, Y1, Y2, Y3, Y4, Y5, Y16, Y17, Y18, Y19, Y20 VCC Power +3.3V G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 13 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Table 9: Pin Identification Signal Name VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VTERM Datasheet VSC834 Function Level Pin A8, A9, B6, B10, B11, B13, B14, C15, D6, D15, F18, M19, R3, U5, U6, U9, V9, V15, W10, W11, W13, W14, W15 H19 G2 J19 J2 N19 M2 P19 N2 R19 B9, B12, F17, W9, W12 Power Power for output channels 0, 2 Power for output channels 1, 3 Power for output channels 4, 6 Power for output channels 5, 7 Power for output channels 8, 10 Power for output channels 9, 11 Power for output channels 12, 14 Power for output channels 13, 15 Power for output channel 16 Termination power GND GND GND GND GND GND GND GND GND GND +2.0V Miscellaneous VCOML VCOMR VHYS U15 V5 V6 Slicing level for Y0 - YN16 (even) Slicing level for Y1 - YN15 (odd) Loss of activity hysterisis threshold ANALOG ANALOG ANALOG Page 14 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC834 Package Information 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring 27mm 256 BGA Package Drawing BOTTOM VIEW g e 10 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 A C E G J H K B D F DETAIL B e g b 0.30 S C A S B S 0.10 S C E1 L M N P R T U V W Y 4 0.10 D CORNER -A-B- DETAIL B D1 A1 c 11 A // ccc C F P TOP VIEW E -C- 5 6 aaa C 45 DEGREE 0.5MM CHAMFER (4 PLCS) DIMENSIONAL REFERENCES NOM. MAX. REF. MIN. 1.65 1.80 A 1.95 0.70 0.65 A1 0.60 26.80 27.00 27.20 D 24.13 (BSC.) D1 26.80 27.00 27.20 E 24.13 (BSC.) E1 0.65 0.75 0.85 b c 1.15 1.25 1.05 20 M 256 N aaa 0.25 ccc 0.25 e 1.27 TYP. 0.15 P g 0.40 0.50 F NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. "e" REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 3. "M" REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE, AND SYMBOL "N" IS THE MAXIMUM ALLOWABLE NUMBER OF BALLS AFTER DEPOPULATING. 4. "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM -C- . 5. DIMENSION "aaa" IS MEASURED PARALLEL TO PRIMARY DATUM -C- . 6. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 7. PACKAGE SURFACE SHALL BE BLACK OXIDE. 8. CAVITY DEPTH VARIOUS WITH DIE THICKNESS 9. SUBSTRATE MATERIAL BASE IS COPPER. 10. BILATERAL TOLENANCE ZONE IS APPLIED TO EACH SIDE OF PACKAGE BODY 11. 45 DEG 0.5 mm CHAMFER CORNER AND WHITE DOT FOR PIN 1 IDENTIFICATION. 12. DIMENSION F IS THE MAX. ENCAP. HEIGHT G52247-0, Rev 4.2 02/09/01 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.5Gb/s 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring Datasheet VSC834 Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC834 Device Type 2.5GHz 17x17 Crosspoint Switch with Input Signal Activity (ISA) Monitoring UB Package Style UB: 256-pin BGA package Notice Vitesse Semiconductor Corporation ("Vitesse") provides this document for informational purposes only. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish any particular task. Vitesse products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 16 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * Email: prodinfo@vitesse.com Internet: www.vitesse.com G52247-0, Rev 4.2 02/09/01 |
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